Performance goals of processors increase in every generation, and progressively more sophisticated architectures are required to implement their complex functions. Advanced architectures require long pipelines operating at very high frequencies. These higher frequencies demand increasing usage of sophisticated circuit design styles like domino.
Domino circuits increase the speed performance of logic circuits by reducing the capacitance associated with the use of P-type metal oxide semiconductors (MOS). Domino circuits accomplish this by precharging a series of logic gates during a first clock phase, or precharge phase, and evaluating the intended logic function during the next clock phase, or evaluation phase. However, domino logic consumes more power than static logic because the domino output precharges every precharge phase and discharges in every evaluation phase when the domino inputs evaluate the output to the discharge state. Thus, unlike static logic, domino logic outputs may toggle even if the inputs do not change.
FIG. 1A represents a prior art domino circuit with nothing to reduce power consumption. A domino logic block 110 is connected to the NMOS evaluation transistor 130, which only allows evaluation while CLK# signal is high. The domino logic block 110 is also connected to the PMOS precharge transistor 120, which pulls the OUT signal 170 high during the precharge phase, while CLK# signal 150 is low. One of the inputs to the domino logic block 110, the IN signal 160, is an output of an upstream logic block. The upstream logic block may be any logic block producing an output. The OUT signal 170 is coupled to a downstream logic block. The downstream logic block may be any logic block having an input.
FIG. 1B represents a timing diagram of the signals used in the circuit illustrated in FIG. 1A. The CLK signal 140 is high during Phase I and low during Phase II. The CLK# signal 150 is the complement of the CLK signal 140. The CLK# signal 150 clocks the domino logic block 110.
The IN signal 160 is an input to the domino logic block 110, and is constant in this example. In this example, the IN signal 160 is illustrated as high, however it may be a low. The OUT signal 170 is the output of the domino logic block 110. The OUT signal 170 is precharged during the precharge phase, while the CLK# signal 150 is low. The OUT signal 170 is evaluated during the evaluation phase, while the CLK# signal 150 is high. In this example, the evaluated output of the domino logic block 110 is low. However, during Phase I, the OUT signal 170 is precharged to a high state. Thus, because of the precharging, the OUT signal 170 toggles every clock cycle. This unnecessarily consumes power.
FIG. 2A represents one prior art method of lowering power consumption using clock gating. A domino logic block 200 has at least one input IN 260. The domino logic block 200 is coupled between an NMOS evaluation transistor 230 and a PMOS precharge transistor 220. Both the NMOS evaluation transistor 230 and the PMOS precharge transistor 220 are driven by the CLK' signal 290. An output LOut 255 of a gating logic block 250 and the CLK signal 140 are connected to the inputs of a NOR gate 240. The CLK' signal 290 is the output of the NOR gate 240. The output of the gating logic block 250 is high when the domino logic 200 does not need to operate.
Thus, when the domino logic block 200 operates, the CLK' signal 290 is the same as the complement of the CLK signal 140. Therefore, the circuit operates identically to the circuit in FIG. 1A. However, when the domino logic block 200 is not needed, the LOut signal 255 is high, thus forcing the CLK' signal 290 to zero. This maintains the domino logic block 200 in the precharged state.
FIG. 2B represents a timing diagram of the signals used in the circuit illustrated in FIG. 2A. The CLK signal 140 is the same as in FIG. 1B. The IN signal 260 is the input to the domino logic block 200. The IN signal 260 is constant, and illustrated as high, in this example. It may be either high or low. The OUT signal 270 is the output of the domino logic block 200. The LOut signal 255 is the output of the gating logic block 250. The LOut signal 255 is a zero when the domino logic block 200 is operating, and a one when the domino logic block 200 is idle. The CLK' signal 290 is the functional NOR of the CLK signal 140 and the LOut signal 255. Therefore, when the LOut signal 255 is low, the CLK' signal 290 is the same as the CLK# signal 150. However, when the LOut signal 255 is high, the CLK' signal 290 is held low or in the precharge state.
In this example, it is assumed that the correct output of the domino logic block 200 is low. Therefore, during normal operation, the domino logic block 200 is precharged during Phase I, and discharged to zero during Phase II. However, when the LOut signal 255 is high, the domino logic block 200 remains in a precharge state and is not discharged. Therefore, the OUT signal 270 remains high as long as the LOut signal 255 is also high. In this way, unnecessary toggling can be avoided while the downstream logic block 210 is busy and the domino logic block 200 is idle.
However, clock gating is difficult to implement. Clock gating may result in clock skew, because of the additional logic in the clocking path, and thereby shift the clock cycle slightly. This causes other logic driven by the clock signal to be shifted with respect to the domino logic block 200. This may cause problems in some timing critical circuits. Further, the turning off and turning on of the gating logic block 250 has to be synchronized with the precharge and discharge cycles. This requires an enable signal which is valid during certain phases of the clock, which requires complex gating logic. Also, in many cases determining when the downstream logic is idle is complicated or impossible, making this method of power conservation unavailable.
Therefore, what is needed is an improved method of lowering power consumption of a domino logic block.